The formation of closely-spaced integrated circuits on the same silicon wafer is well known, as is technology for conductive interconnection of such circuits. By way of example, one often required interconnect is the wiring of the gate of a Complementary Metal Semiconductor (CMOS) Field-Effect Transistor (FET) to the diffusion of an adjacent FET. Another common, but more complicated interconnection is that between adjacent diffusions of an FET, without a conductive contact to the intervening gate.
Traditional interconnection techniques use contact holes and wire metallurgy to form desired wiring levels. Such techniques typically involve the deposition of a conformal metal layer(s) over the devices and/or substrates, and a subsequent etch of the metal layer(s) from areas not requiring electrical contact. One such interconnection technique is described in detail in U.S. Pat. No. 4,933,743 entitled "HIGH PERFORMANCE INTERCONNECT SYSTEM FOR AN INTEGRATED CIRCUIT." Briefly, a technique is described therein in which contact holes are etched from a dielectric layer to expose device contact areas. A conformal metal layer is formed over the structure, patterned and then etched to form a level of interconnect. Unfortunately, the non-planar surfaces formed by etching the conformal metal layer complicate the subsequent formation of additional layers or devices.
A recent alternative approach, referred to as local interconnect(s), begins with an insulator being blanket-deposited over a substrate and any devices formed thereon. This blanket insulator is then selectively etched to expose desired device contacts. An inlaid metal structure is deposited in the etched region to electrically contact the exposed device contacts. This metal structure is then planarized with the remaining insulator. The local interconnection technique is used to electrically contact devices beneath the first wiring level, which is formed as described above. The technique avoids problems associated with multiple wiring layers. In particular, the inlaid metal has less resistance, supports connections of very short lengths and is generally stronger than conformal wiring. One specific embodiment of the local interconnect technique is described in U.S. Pat. No. 4,789,648, entitled "METHOD FOR PRODUCING COPLANAR MULTI-LEVEL METAL/INSULATOR FILMS ON A SUBSTRATE AND FOR FORMING PATTERNED CONDUCTIVE LINES SIMULTANEOUSLY WITH STUD VIAS," assigned to the same assignee as the present application. The etch and mask sequences described therein are generally known in the art as damascene techniques and sometimes referred to herein as "damascening".
Currently, a necessary result of this technique is that the inlaid metal structure, or stud, will electrically contact all gate stacks of the devices exposed by the insulator etch. Multiple gates or diffusions may be exposed and thus contacted. Using selective etching, an effective interconnect between a gate and an adjacent diffusion is possible. However, a local interconnection between diffusions that remains insulated from the intervening gate has not been accomplished.
A need therefore exists for techniques that will allow an inlaid, local interconnect to selectively contact certain gate stacks and remain insulated from others. The techniques should offer a circuit designer flexibility and provide options based on available processing technologies. The resulting structures should have precisely-formed, predictable shapes and electrical characteristics. Further, the fabrication technique should not diminish the electrical response of current circuit designs, and should not involve overly complex fabrication steps.